1. Field of the Invention
The present invention relates to a metal oxide semiconductor field effect transistor (MOSFET), a semiconductor device including the MOSFET, and a method for making the MOSFET. In particular, it relates to a power MOSFET, a semiconductor device including the power MOSFET, and a method for making the power MOSFET.
2. Description of the Related Art
Power supplies of various electronic apparatuses have been provided with voltage transducers that increase or decrease the power supply voltage output from the power supplies according to the usage. These transducers have been provided with power MOSFETs that function as switching elements or the like configured to feed power supply voltage supplied from the power supply to various electrical circuits downstream by being turned ON or OFF based on predetermined control signals.
This power MOSFET is shown in FIG. 9A. As shown in FIG. 9A, a power MOSFET 100 includes a semiconductor substrate 101; a well region 103 of a first conductivity type formed by implanting ions of an impurity of a first conductivity type (P-type) into the semiconductor substrate 101 through an insulating film and then thermally diffusing the implanted ions; a source region 110a and a drain region 110b formed by implanting ions of an impurity of a second conductivity type (N-type) into the well region 103 such that the two regions are a predetermined distance away from each other; and a gate electrode 105 formed on a gate insulating film 104 on the surface of the well region 103 in the region between the source region 110a and the drain region 110b (for example, refer to Japanese Unexamined Patent Application Publication No. 11-298000). The power MOSFET also includes lightly doped drain (LDD) regions 108.
The power MOSFET 100 is configured such that by applying a predetermined control signal (gate voltage) to the gate electrode 105, electrical current corresponding to the gate voltage flows between the source region 110a and the drain region 110b. 
This type of power MOSFET 100 is usually installed in a section involving relatively high voltage and relatively large electric current, such as power supplies as described above and is thus desired to achieve relatively high rated voltage and relatively high rated current.
One of the means for evaluating the rated voltage and the rated current is unclamped inductive switching (UIS) that indicates avalanche resistance.
In order to conduct evaluation by UIS, as shown in FIG. 9B, the power MOSFET 100 is first turned on to allow electric current Id to flow between the drain region 110b and the source region 110a while connecting the drain region of the power MOSFET 100 to a power supply Vdd through a coil L.
By adjusting the length of time of holding the power MOSFET 100 ON, the value of the electric current Id can be controlled. The electric current Id increases with the length of time.
After the power MOSFET 100 is turned OFF, the electric current Id still keeps flowing because of the characteristics of the coil L. The power MOSFET 100 allows the electric current Id to continuously flow while undergoing avalanche breakdown. Then, after the energy stored in the coil L while the power MOSFET is being turned ON is completely released, the power MOSFET 100 enters a typical OFF-state in which electric current Id no longer flows between the source region 110a and the drain region 110b. 
However, if the electric current Id is a particular value of more, avalanche breakdown no longer occurs in the power MOSFET 100, resulting in breaking of the power MOSFET.
This is attributable to the following mechanism. When the power MOSFET 100 is switched from the ON state to the OFF state, the electric current Id flows from the drain region 110b to the source region 110a due to the avalanche breakdown of the power MOSFET 100 for some while. During this process, an NPN-type bipolar transistor is parasitically formed by the N-type drain region 110b, the P-type well region 103 under the gate electrode 105, and the N-type source region 110a. When the value of the electric current Id is elevated to a predetermined level or more, a potential of a predetermined value of more is generated in the base (the well region 103 under the gate electrode) of this NPN-type bipolar transistor. This causes the NPN-type bipolar transistor to enter the ON state, and short-circuiting of the drain region 110b and the source region 110a occurs although no gate voltage is applied to the gate electrode 105 of the power MOSFET 100, thereby resulting in breaking of the power MOSFET 100.
In other words, the value of the electric current Id at the time of breaking of the power MOSFET 100 and the value of the voltage applied to the drain region 110b at this time are the rated current and the rated voltage of the power MOSFET 100, respectively.